1. Technical Field
The present invention relates to clocked inverter circuits, latch circuits, shift register circuits, drive circuits for display apparatuses, and display apparatuses, and is applicable to, for example, flat display apparatuses including organic EL (electroluminescence) devices. The present invention relates to a technology in which switching circuits implemented by a set of transistors that switch operations in a complementary manner form a series circuit, an output of the connection midpoint of the series circuit is output to an inverter circuit, an input signal is input to one end of the series circuit, and a signal that is output from an inverter circuit and that corresponds to the output of the connection midpoint of the series circuit is supplied to an opposite end of the series circuit, thereby allowing an operation using only single-channel transistors.
2. Background Art
Conventionally, in a flat display apparatus, a shift register circuit provided in a vertical drive circuit sequentially transfers drive signals to generate drive signals for pixels, for example, as disclosed in Japanese Unexamined Patent Application Publication No. 5-265411. Such a shift register circuit is formed by serially connecting latch circuits for latching input signals with reference to clocks and outputting the resulting signals, for example, as disclosed in Japanese Unexamined Patent Application Publication No. 5-241201.
FIG. 1 is a wiring diagram showing the latch circuit. In this latch circuit 1, P-channel MOS transistors TR1 and TR2 and N-channel MOS transistors TR3 and TR4 are connected in series between a power supply Vcc and ground. As shown in part (A) in FIG. 2, an input signal IN is input from the previous stage to the transistor TR1 at the power-supply side and the transistor TR4 at the ground side, and a clock CK and a clock CKX, which is an invert signal of the clock CK, are input to the corresponding inner transistors TR2 and TR3 (parts (B) and (C) in FIG. 2). The transistors TR1 to TR4 form a clocked inverter circuit 2 that operates with reference to the clock CK.
Similarly, P-channel MOS transistors TR5 and TR6 and N-channel MOS transistors TR7 and TR8 are connected in series between a power supply Vcc and the ground. In a manner opposite to the transistors TR1 and TR4, the clock CKX and the clock CK are input to the corresponding inner transistors TR6 and TR7. Thus, the transistors TR5 to TR8 form a clocked inverter circuit 3 that operates with reference to the clock CKX having the reverse polarity of the clock CK.
In the latch circuit 1, outputs of the clocked inverter circuits 2 and 3 are input to an inverter circuit 4, in which a P-channel MOS transistor TR9 and an N-channel MOS transistor TR10 are connected in series between a power supply Vcc and the ground. An output of the inverter circuit 4 is fed back to an input of the clocked inverter circuit 3. With this arrangement, a latch circuit for latching the input signal IN based on the clock CK is formed. An output OUT (part (D) in FIG. 2) of the inverter circuit 4 is output to the next stage.
The shift register circuit is formed in such a manner that the latch circuits 1 for latching the input signal IN in response to the rising of such a clock CK and latch circuits in which the connections of the clock CK and the CKX are interchanged relative to the latch circuits 1 are alternately connected in series. A drive signal generated by the timing generator is supplied to the latch circuit at the first stage and is sequentially transferred, so that a drive signal for each pixel is generated.
The latch circuits constituting such a shift register have a drawback in that it is difficult to fabricate the latch circuits using amorphous silicon TFTs (thin film transistors), which can be formed on a glass substrate. That is, the amorphous silicon TFTs (thin film transistors) exhibit a small mobility, about 1/100th of that of transistors containing single-crystal silicon or polysilicon, thus posing a drawback in that P-channel transistors cannot be fabricated.
In a flat display apparatus in which pixels are configured using amorphous silicon, a pixel section in which the pixels are arranged is formed on a glass substrate and drive circuits fabricated in a separate process by using single-crystal silicon or polysilicon are connected to the pixel section on the glass substrate.
That is, as shown in FIG. 3, in a flat display apparatus 11 of such a type, a pixel section 12 in which pixels are arranged in a matrix is formed on a glass substrate 13. In a separate process, integrated circuits including vertical drive circuits 14A and 14B for sequentially driving the pixels of the pixel section 12 line by line are formed, using single-crystal silicon, polysilicon, or the like, by shift registers. The integrated circuits including the vertical drive circuits 14A and 14B are then arranged at the circumference of a glass substrate 13 in conjunction with the integrated circuit of a horizontal drive circuit 15 for setting the gradations of the pixels.
If such drive circuits including the sift register circuits can be fabricated using TFTs containing amorphous silicon, such drive circuits and the pixels can be integrally formed on a glass substrate. Correspondingly, it would be possible to simplify the manufacturing process of such a flat display panel apparatus. To this end, it is necessary to provide clocked inverter circuits and latch circuits that operate only with single-channel transistors that can be created using amorphous-silicon TFTs.